Experimental the cross-sectional in Figure (1-b) the NMOS transistor

Experimental Procedure

In this section, we will
discuss the basic structure of CMOS or simply MOS. There is
tow type of coms structure, the NMOS and
PMOS transistors. CMOS
integrated circuits are fabricated on thin circular slices of silicon wafers. here we will cover the NMOS type because
both transistors are complementary in nature. in a groundwork way, to any layer that
we need to pattern. We start out with an unprocessed wafer, as
illustration in Figure (1-a).

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Figure (1-a) a clean bare wafer

Figure( 1-b) a p-substrate

 in the cross-sectional in Figure (1-b) the NMOS transistor is fabricated on a P-type substrate and the PMOS
transistor is fabricated in N-well. after
put the P-type substrate, we grow an oxide on it such as Si02 or glass (see
figure 1-c). However, semiconductor processes must have precisely thickness and
purity of the oxide.

Figure( 1-c) The oxidation process

 The next step of the generic
CMOS patterning is adding A light-sensitive layer across the wafer it’s called
as Photoresist layer shown in figure (1-d). notes that the dimensions of the
layers that is oxide, resist, and the wafer, are not drawn to scale. because the normal thickness of a
wafer is (typically between 500 µm and 800 µm), while the thickness of a grown oxide or Photoresist
layer is may be only a µm (

) or even less. When It is formed we
moved to the masking step which is formed from layout program (see figure 1-f),
and it use a reticle mask which is known as single mask, however you can see
there is a use of selectively illuminating apply in the areas of the wafer shown
figure (1-g).

Figure( 1-f) the masking process