Now a day’s data storage is gainingmore importance in human life. All electronic and digital devices need memoryfor reducing the power consumption. The concept of “more data in less space” isuseful for increasing the system performance and overall system efficiency.Generally we used semiconductor memory as “SRAM”.
SRAM can be abbreviated”Static Random Access Memory”. Many VLSI chip can have SRAM memory because oftheir large storage capacity and fast accessing time. Where the word staticindicates that it does not need to be habitually refreshed but the DRAM need habituallyrefreshed. DRAM can be abbreviated as “Dynamic Random Access Memory” which isanother type of memory. Both the memories can be classified from “Random AccessMemory: (RAM).
In this paper the poweranalysis of 6 transistor SRAM is compared with 7 transistor SRAM. As a result the power dissipation of 7transistors is high when compared with 6 transistors. The power dissipation of6T SRAM is about 2.991mW and the power dissipation of 7T SRAM is about 3.183Mw.SRAM are mostly used for mobile applications, because of their ease of use andlow leakage of power. In this paper the schematic of 6T SRAM and 7T SRAM aredrawn using DSCH software and the layouts are drawn using MICROWIND software.
Inrecent days, Static Random Access Memory has become the major part in digitalworld. Because which occupies the largest portion of SOC (system-on-chip). Thedevice need SRAM memory mainly for device dissipate small amount of power. Butthe dynamic power dissipation causes problems in digital circuits because thedynamic power depends on supply voltage, switching frequency and output voltageswing. Dynamic power dissipation can be minimized by reducing the supplyvoltage. At the same time low supply voltage leads to performance degradationand also decreases the threshold voltage which in turn increases the subthreshold current hence the static power dissipation increases.
This paperdiscuss about the power dissipation of 6 transistors and 7 transistors SRAM. Italso includes the functional view of 6T and 7T SRAM cells. A conventional 6T SRAMconsists 6 transistors which form two cross coupled inverters.
This bit cellcan be read and write single bit data. When a bit is stored in memory the 6TSRAM behave like a latch. The cross coupled inverter pattern which causes largearea consumption which is a drawback of 6T SRAM when compared to resistive load.Conventional SRAM with 6 transistors is shown in figure 1 and 6T SRAM havethree states they are read, write and hold states.